{"id":5736,"date":"2023-12-08T10:00:52","date_gmt":"2023-12-08T09:00:52","guid":{"rendered":"https:\/\/msxitalia.org\/?p=5736"},"modified":"2023-12-08T15:29:38","modified_gmt":"2023-12-08T14:29:38","slug":"i-registri-della-cpu-z80","status":"publish","type":"post","link":"https:\/\/msxitalia.org\/en\/i-registri-della-cpu-z80\/","title":{"rendered":"The Z80 CPU registers \u2013 handout 2"},"content":{"rendered":"<p>What you are about to read is a handout and certainly not a book and therefore does not claim to be exhaustive and self-sufficient. This can be accompanied by documentation that can be easily found both in paper and digital form. For the drafting of this handout, in addition to the obvious information that can be found online, I took extensive inspiration from the Z80 Programming in Assembly language manuals and the New Z80 manual. As with all my other articles I apologize for any inaccuracies. Enjoy the reading.<\/p>\n<p>INTERNAL STRUCTURE OF THE CPU<\/p>\n<p>REGISTERS<br \/>\nThe figure illustrates the register set of the Z80 CPU. All registers are implemented using static RAM. As we can see the CPU integrates two sets of six generic registers that can be used individually as 8-bit registers or in pairs as 16-bit registers and two sets of accumulator and flag registers. These, as can be seen from the figure, are called Main Register and Alternate Register. There are also six registers for special uses. Below we will see in detail the function of each register.<img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/set-registri-z80-300x190.png\" class=\"wp-image-5738 size-medium aligncenter lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"Set registri CPU Z80\" width=\"300\" height=\"190\" \/><noscript><img decoding=\"async\" class=\"wp-image-5738 size-medium aligncenter\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/set-registri-z80-300x190.png\" alt=\"Set registri CPU Z80\" width=\"300\" height=\"190\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/set-registri-z80-300x190.png 300w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/set-registri-z80-18x12.png 18w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/set-registri-z80.png 459w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/noscript><\/p>\n<h5>SPECIAL REGISTERS<\/h5>\n<p>Below we describe the set of registers defined as special within the Z80 CPU.<\/p>\n<p><strong>PROGRAM COUNTER (PC)<\/strong><br \/>\n<img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/PC.png\" class=\"size-full wp-image-5742 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"165\" height=\"31\" \/><noscript><img decoding=\"async\" class=\"size-full wp-image-5742 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/PC.png\" alt=\"\" width=\"165\" height=\"31\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/PC.png 165w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/PC-18x3.png 18w\" sizes=\"(max-width: 165px) 100vw, 165px\" \/><\/noscript>This register contains the 16-bit address of the instruction to be loaded into memory. The PC is automatically incremented whenever its contents are transferred to the address lines. When there is a jump in the program, the new address value is placed in the PC, instead of performing the automatic increment operation.<\/p>\n<p><strong>STACK POINTER (SP)<br \/>\n<\/strong><img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/SP.png\" class=\"size-full wp-image-5743 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"160\" height=\"32\" \/><noscript><img decoding=\"async\" class=\"size-full wp-image-5743 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/SP.png\" alt=\"\" width=\"160\" height=\"32\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/SP.png 160w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/SP-18x4.png 18w\" sizes=\"(max-width: 160px) 100vw, 160px\" \/><\/noscript>This register contains the 16 bit address of the last element of a stack, located in any part of the memory external to the processor. The stack is organized in LIFO (Last-In-First-Out) fashion. Data can be inserted or extracted from the stack (through a generic register) using PUSH or POP instructions.<\/p>\n<p><strong>INDEX REGISTER (IX, IY)<\/strong><\/p>\n<p><strong><img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/IX.png\" class=\"size-full wp-image-5741 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"176\" height=\"84\" \/><noscript><img decoding=\"async\" class=\"size-full wp-image-5741 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/IX.png\" alt=\"\" width=\"176\" height=\"84\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/IX.png 176w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/IX-18x9.png 18w\" sizes=\"(max-width: 176px) 100vw, 176px\" \/><\/noscript><\/strong>The two independent index registers contain a 16-bit base address that is used in indexed addressing modes. In this mode, an index register is used as a basis to point to a region of memory where data is to be stored or retrieved. An additional byte specifying the displacement from the base is included in the instruction that uses this type of addressing. The final address is then obtained by adding the specified displacement to the starting address (contained in the index register). The displacement is expressed as a two&#039;s complement signed binary number.<\/p>\n<p><strong>INTERRUPT PAGE ADDRESS REGISTER (I)<br \/>\n<\/strong><img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/i.png\" class=\"size-full wp-image-5746 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"82\" height=\"27\" \/><noscript><img decoding=\"async\" class=\"size-full wp-image-5746 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/i.png\" alt=\"\" width=\"82\" height=\"27\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/i.png 82w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/i-18x6.png 18w\" sizes=\"(max-width: 82px) 100vw, 82px\" \/><\/noscript>This register contains the 8 most significant bits of the address of the interrupt response routines. The 8 least significant bits are provided directly by the device that generated the interrupt. This allows an extremely fast response to be generated but above all it allows the interrupt management programs to be positioned dynamically anywhere in the memory, while the access time to the aforementioned programs remains minimal in any case.<\/p>\n<p><strong>MEMORY REFRESH REGISTER (R)<\/strong><br \/>\n<img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/r.png\" class=\"size-full wp-image-5745 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"82\" height=\"29\" \/><noscript><img decoding=\"async\" class=\"size-full wp-image-5745 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/r.png\" alt=\"\" width=\"82\" height=\"29\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/r.png 82w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/r-18x6.png 18w\" sizes=\"(max-width: 82px) 100vw, 82px\" \/><\/noscript>The Z80 contains a memory refresh counter, to facilitate the use of dynamic memories. Seven of the 8 bits of this register are automatically incremented after each read of an instruction. Its content is sent on the addressing BUS together with the REFRESH signal, to obtain the refresh of the dynamic memories. This operation is totally transparent to the program and does not slow down its execution.<\/p>\n<h5>GENERAL USE REGISTERS<\/h5>\n<p>The remaining registers are divided into two interchangeable groups, one defined as the main register bank and the other as the alternative register bank (in the figure at the beginning of the handout they are shown as Main register and Alternate register but the meaning does not change). Through the exchange instructions, the programmer can select the bank of registers on which he wants to operate.<\/p>\n<p><strong>ACCUMULATOR <\/strong><\/p>\n<p><img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/a.png\" class=\"size-medium wp-image-5748 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"169\" height=\"29\" \/><noscript><img decoding=\"async\" class=\"size-medium wp-image-5748 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/a.png\" alt=\"\" width=\"169\" height=\"29\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/a.png 169w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/a-18x3.png 18w\" sizes=\"(max-width: 169px) 100vw, 169px\" \/><\/noscript>There are two independent 8-bit accumulators in the CPU with their flag registers. The accumulator contains the result of an arithmetic\/logical operation while the flag register indicates specific conditions for the operations performed (for example whether the result of an operation is zero or not).<\/p>\n<p><strong>REGISTER FLAG<br \/>\n<\/strong>The Flag register is structured as shown in the figure, depending on the documentation you read, the memonic names may be slightly different, but their meaning remains unchanged.<br \/>\nStarting from the least significant bit we find:<\/p>\n<ul>\n<li>Bit 0 (C) \u2013 This is the carry flag which is typically set to 1 when a carry occurs on the last bit. It is also altered by shift operations and logical operations.<\/li>\n<li>Bit 1 (N) \u2013 This is the N flag that is set when a subtraction or decrement is performed. It cannot be tested using conditional jumps, but is exploited by the DAA operation.<\/li>\n<li>Bit 2 (P\/V) \u2013 This is the parity or overflow flag. When it works as a parity flag (generally in logical operations and shifts) it is set to one when the number of bits set to 1 in the result is even. If it works as an overflow flag (generally in arithmetic operations) it is set to 1 when the sign of the result is incorrect.<\/li>\n<li>Bit 3 \u2013 It has no meaning.<\/li>\n<li>Bit 4 (H) \u2013 This is the half-carry flag and indicates the carry that occurs at bit 3 of the accumulator. It cannot be tested with conditional branch instructions, but is exploited by the DAA operation.<\/li>\n<li>Bit 5 \u2013 It has no meaning.<\/li>\n<li>Bit 6 (Z) \u2013 It is the zero flag: it is set to 1 when the result of an operation is 0.<\/li>\n<li>Bit 7 (S) \u2013 This is the sign flag. When it is set to 1 it means that the result of the operation is negative (in other words the most significant bit of the result is equal to 1).<\/li>\n<\/ul>\n<p><img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/f-300x198.png\" class=\"alignnone size-medium wp-image-5749 lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"300\" height=\"198\" \/><noscript><img decoding=\"async\" class=\"alignnone size-medium wp-image-5749\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/f-300x198.png\" alt=\"\" width=\"300\" height=\"198\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/f-300x198.png 300w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/f-18x12.png 18w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/f.png 428w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/noscript><\/p>\n<p><strong>\u00a0<\/strong><strong>GENERAL PURPOSE REGISTER<\/strong><br \/>\n<img decoding=\"async\" data-src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/g.png\" class=\"size-full wp-image-5750 alignleft lazyload\" src=\"data:image\/gif;base64,R0lGODlhAQABAIAAAAAAAP\/\/\/yH5BAEAAAAALAAAAAABAAEAAAIBRAA7\" alt=\"\" width=\"166\" height=\"95\" \/><noscript><img decoding=\"async\" class=\"size-full wp-image-5750 alignleft\" src=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/g.png\" alt=\"\" width=\"166\" height=\"95\" srcset=\"https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/g.png 166w, https:\/\/msxitalia.org\/wp-content\/uploads\/2023\/12\/g-18x10.png 18w\" sizes=\"(max-width: 166px) 100vw, 166px\" \/><\/noscript>The CPU contains six general-purpose 8-bit registers. These registers have the particularity of being able to be used individually as an 8-bit register, or in pairs as 16-bit registers. As can be seen from the figure, the register pairs are BC, DE and HL.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>IFF REGISTER<br \/>\n<\/strong>The IFF (Interrupt Flip-Flop) register is a special 1-bit register that is used to enable or disable hardware interrupts. The IFF register is divided into two parts: IFF1 and IFF2. IFF1 is used to indicate whether interrupts are enabled or not, while IFF2 is used to save the state of IFF1 during the execution of an interrupt service routine.<\/p>\n<p>&nbsp;<\/p>\n<p>If you are interested you can find it here\u00a0<a href=\"https:\/\/msxitalia.org\/en\/pinout-della-cpu-z80\/\">third dispensation<\/a>.<\/p>","protected":false},"excerpt":{"rendered":"<p>Questa che vi apprestate a leggere \u00e8 una dispensa e non certamente un libro e quindi non ha la pretesa di essere esaustiva e autosufficiente. Questa pu\u00f2 essere affiancata alla documentazione che \u00e8 possibile reperire facilmente sia in forma cartacea sia in forma digitale. Per la stesura di questa dispensa oltre alle ovvie informazioni che [&hellip;]<\/p>\n","protected":false},"author":3,"featured_media":5737,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_et_pb_use_builder":"","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"categories":[6,26],"tags":[],"dipi_cpt_category":[],"class_list":["post-5736","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-hardware","category-z80"],"_links":{"self":[{"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/posts\/5736","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/comments?post=5736"}],"version-history":[{"count":24,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/posts\/5736\/revisions"}],"predecessor-version":[{"id":5883,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/posts\/5736\/revisions\/5883"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/media\/5737"}],"wp:attachment":[{"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/media?parent=5736"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/categories?post=5736"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/tags?post=5736"},{"taxonomy":"dipi_cpt_category","embeddable":true,"href":"https:\/\/msxitalia.org\/en\/wp-json\/wp\/v2\/dipi_cpt_category?post=5736"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}